夏至未至经典语录-

2021年2月15日发(作者：黑与白歌词)

APPLICATION

SJA1000

Stand-alone CAN controller

1. INTRODUCTION

The SJA1000 is a stand-alone CAN Controller product with advanced features

for use in automotive and general industrial applications. It is intended to replace the

PCA82C200 because it is hardware and software compatible. Due to an enhanced set

of functions this device is well suited for many applications especially when system

optimization, diagnosis and maintenance are important.

This report is intended to guide the user in designing complete CAN nodes based

on

the

SJA1000.

The

report

provides

typical

application

circuit

diagrams

and

flow

charts for programming.

2. OVERVIEW

The

stand-alone

CAN

controller

SJA1000

1

h

as

two

different

Modes

of

Operation:

- BasicCAN Mode (PCA82C200 compatible)

- PeliCAN Mode

Upon

Power-up

the

BasicCAN

Mode

is

the

default

mode

of

operation.

Consequently, existing hardware and software developed for the PCA82C200 can be

used without any change. In addition to the functions known from the PCA82C200 ,

some extra features have been implemented in this mode which make the device more

attractive. However, they do not influence the compatibility to the PCA82C200.

The PeliCAN Mode is a new mode of operation which is able to handle all frame

types according to CAN specification 2.0B

8. Furthermore it provides a couple of

- 1 -

enhanced

features

which

makes

the

SJA1000

suitable

for

a

wide

range

of

applications.

2.1 SJA1000 Features

The features of the SJA1000 can be clustered into three main groups:

Well-established PCA82C200 Functions

Features of this group have already been implemented in the PCA82C200.

Improved PCA82C200 Functions

Partly

these

functions

have

already

been

implemented

in

the

PCA82C200.

However,

in

the

SJA1000

they

have

been

improved

in

terms

of

speed,

size

or

performance.

Enhanced Functions in PeliCAN Mode

In

PeliCAN

Mode

the

SJA1000

offers

a

couple

of

Error

Analysis

Functions

supporting

diagnosis,

system

maintenance

and

optimization.

Furthermore

functions

for general CPU support and System Self Test have been added in this mode.

In

the

following

table

all

SJA1000

features

are

listed

including

their

main

benefits for the application.

Table 1: SJA1000 Features with benefits for the application

Well-established PCA82C200 Functions

- 2 -

Improved PCA82C200 Functions

2.2 CAN Node Architecture

Generally each CAN module can be divided into different functional blocks. The

connection to the CAN bus linesis usually built with a CAN Transceiver optimized

for the applications [3], [4], [5]. The transceiver controls the logic level signals from

the CAN controller into the physical levels on the bus and vice versa.

The next upper level is a CAN Controller which implements the complete CAN

protocol

defined

in

the

CAN

nSpecification

[8].

Often

it

also

covers

message

buffering and acceptance filtering.

All these CAN functions are controlled by a Module Controller which performs

- 3 -

the functionality of the application. For example, it controls actuators, reads sensors

and handles the man-machine interface (MMI).

As shown in Figure 1 the SJA1000 stand-alone CAN controller is always located

between a microcontroller and the transceiver, which is an integrated circuit in most

cases.

2.3 Block Diagram

The following figure shows the block diagram of the SJA1000.

- 4 -

The

CAN

Core

Block

controls

the

transmission and

reception

of

CAN

frames

according to the CAN specification.

The

Interface

Management

Logic

block

performs

a

link

to

the

external

host

controller which can be a microcontroller or any other device. Every register access

via

the

SJA1000

multiplexed

address/data

bus

and

controlling

of

the

read/write

strobes is handled in this unit. Additionally to the BasicCAN functions known from

the

PCA82C200, new PeliCAN features have been added. As a consequence of this,

additional registers and logic have been

implemented mainly in this block.

The

Transmit

Buffer

of

the

SJA1000

is

able

to

store

one

complete

message

(Extended or Standard).

Whenever a transmission is

initiated by the host controller

the

Interface

Management

Logic

forces

the

CAN

Core

Block

to

read

the

CAN

message from the Transmit Buffer.

When receiving a message, the CAN Core Block converts the serial bit stream

into

parallel

data

for

the

Acceptance

Filter.

With

this

programmable

filter

the

SJA1000 decides which messages actually are received by the host controller.

All

received

messages

accepted

by

the

acceptance

filter

are

stored

within

a

Receive

FIFO.

Depending

on

the

mode

of

operation

and

the

data

length

up

to

32

messages

can be stored. This

enables

the

user to

be more flexible when specifying

interrupt

services

and

interrupt

priorities

for

the

system

because

the

probability

of

dataoverrun conditions is reduced extremely.

3. SYSTEM

For

connection

to

the

host

controller,

the

SJA1000

provides

a

multiplexed

address/data

bus

and

additional

read/write

control

signals.

The

SJA1000

could

be

seen as a peripheral memory mapped I/O device for the host controller.

3.1 SJA1000 Application

Configuration

Registers

and

pins

of

the

SJA1000

allow

to

use

all

kinds

of

integrated or discrete CAN transceivers. Due to the flexible microcontroller interface

- 5 -

applications with different microcontrollers are possible.

3.2 Power Supply

The SJA1000 has three pairs of voltage supply pins which are used for different

digital and analog internal blocks of the CAN controller.

VDD1 / VSS1: internal logic (digital)

VDD2 / VSS2: input comparator (analog)

VDD3 / VSS3: output driver (analog)

The

supply

has

been

separated

for

better

EME

behaviour.

For

instance

the

VDD2 can be de-coupled via an RC filter for noise suppression of the comparator.

3.3 Reset

For a proper reset of the SJA1000 a stable oscillator clock has to be provided at

XTAL1 of the CAN controller, see also chapter 3.4. An external reset on pin 17 is

synchronized and internally lengthened to 15 tXTAL. This guarantees a correct reset

of all SJA1000 registers (see [1]). Note that an oscillator start-up time has to be taken

into account upon power-up.

3.4 Oscillator and Clocking Strategy

The

SJA1000

can

operate

with

the

on-chip

oscillator

or

with

external

clock

sources. Additionally the CLK OUT pin can be enabled to output the clock frequency

for

the

host

controller.

Figure

4

shows

four

different

clocking

principles

for

applications

with

the

SJA1000.

If

the

CLK

OUT

signal

is

not

needed,

it

can

be

switched off with the Clock Divider register (Clock Off = 1). This will improve the

EME performance of the CAN node.

The frequency of the CLK OUT signal can be changed with the Clock Divider

Register:

f

CLKOUT

= f

XTAL

/ Clock Divider factor (1,2,4,6,8,10,12,14).

- 6 -

Upon power up or hardware reset the default value for the Clock Divider factor

depends on the selected interfacemode (pin 11). If a 16 MHz crystal is used in Intel

mode,

the

frequency

at

CLK

OUT

is

8

MHz.

In

Motorola

mode

a

Clock

Divider

factor of 12 is used upon reset which results in 1,33 MHz in this case.

3.5 CPU Interface

The

SJA1000

supports

the

direct

connection

to

two

famous

microcontroller

families: 80C51 and 68xx. With the MODE pin of the SJA1000 the interface mode is

selected.

Intel Mode: MODE = high

Motorola Mode: MODE = low

The connection for the address/data bus and the read/write control signals in

both Intel and Motorola mode is shown in Figure 5. For Philips 8-bit microcontrollers

based on the 80C51 family and the 16-bit microcontrollers with XA architecture the

Intel Mode is used.

4. CONTROL OF CAN COMMUNICATION

4.1 Basic Functions and Registers for Controlling the SJA1000

The functionality with respect to configuration and activities of the SJA1000 is

given by the program of the host mcontroller. Thus the SJA1000 is tailored to meet

the

requirements

of

CAN-bus

systems

with

different

properties.

The

data

exchange

between

the

host

controller

and

the

SJA1000 is

done

via

a

set

of

registers

(control

segment) and a RAM (message buffer). The registers and an address window to a part

of

the

RAM,

making

up

the

Transmit

and

Receive

Buffers,

appear

to

the

host

controller as peripheral registers.

Table 2 lists these registers grouped according to their usage in a system.

Note,

that

some

registers

are

available

in

PeliCAN

mode

only

and

that

the

Control

Register

is

available

in

BasicCAN

mode

only.

Furthermore

some

registers

- 7 -

are read only or write only and some can be accessed during Reset Mode only.

More information about the registers with respect to read and/or write access, bit

definition and reset values, can be found in the data sheet

1

.

Table 2: Classification of the internal registers of the SJA1000

4.1.1 Transmit Buffer / Receive Buffer

The data to be transmitted on the CAN bus is loaded into the memory area of the

SJA1000, called “Transmit

Buffer”. The data received from the CAN bus is stored in

the memory area of the SJA1000, called “Receive

Buffer”. These buffers contains 2,

3 or 5 bytes for the identifier and frame information (dependent on mode and frame

type)

and

up

to

8

data

bytes.

For

further

information

about

the

definition

and

composition of the bits in the message buffers see the data sheet [1].



B

asicCAN mode: The buffers are 10

-bytes long (see Table 3).

–

2 identifier bytes

- 8 -

–

up to 8 data bytes.



P

eliCAN mode: The buffers are 13 bytes long (see Table 4).

–

1 byte for Frame Information

–

2 or 4 identifier bytes (Standard Frame or Extended Frame)

–

up to 8 data bytes.

Table 3: Layout of Rx- and Tx-Buffer in BasicCAN mode

Table 4: Layout of Rx-1. (read access) and Tx-Buffer (write access2.) in PeliCAN

mode

1. The whole Receive FIFO (64 bytes) can be accessed using the CAN addresses

32 to 95(see also chapter 5.1).

2. A read access of the Tx-Buffer can be done using the CAN addresses 96 to

108 (see also chapter 5.1)

4.1.2 Acceptance Filter

The

stand-alone

CAN

controller

SJA1000

is

equipped

with

a

versatile

acceptance filter, which

allows an

automatic check of the identifier and

data bytes.

Using these effective filtering methods, messages or a group of messages not valid for

- 9 -

a certain node can be prevented from being stored in the Receive Buffer. Thus it is

possible to reduce the processing load of the host controller.

The filter is controlled by the acceptance code and mask registers according to

the algorithms given in the data sheet

1. The received data is compared bitwise

with

the

value

contained

in

the

Acceptance

Code

register.

The

Acceptance

Mask

Register defines the bit positions, which are relevant for the comparison (0 = relevant,

1 = not relevant). For accepting a message all relevant received bits have to match the

respective bits in the Acceptance Code Register.

Acceptance Filtering in BasicCAN Mode

This

mode

is

implemented

in

the

SJA1000

as

a

plug-and-play

replacement

(hardware

and

software)

for

the

PCA82C200.

Thus

the

acceptance

filtering

corresponds

to

the

possibilities,

which

were

found

in

the

PCA82C200

7.

The

filter

is

controlled

by

two

8-bit

wide

registers

–

Acceptance

Code

Register

(ACR)

andAcceptance Mask Register (AMR). The 8 most significant bits of the identifier of

the CAN message are compared to the values

contained

in

these

registers,

see

also

Figure

8.

Thus

always

groups

of

eight

identifiers can be defined to beaccepted for any node.

Acceptance Filtering in PeliCAN Mode

The acceptance filtering has been expanded for the PeliCAN mode: Four 8-bit

wide Acceptance Code registers (ACR0, ACR1, ACR2 and ACR3) and Acceptance

Mask

registers

(AMR0,

AMR1,

AMR2

and

AMR3)

are

available

for

a

versatile

filtering of messages. These registers can be used for controlling a single long filter or

two shorter filters, as shown in Figure 9 and Figure 10. Which bits of the message are

used for the acceptance filtering, depend on the received frame (Standard or Extended)

and on the selected filter mode (single or dual filter). Table 5 gives more information

about which bits of the message are compared with the Acceptance Code and Mask

bits. As it is seen from the figures and the table, it is possible to include the RTR bit

and even data bytes in the acceptance filtering for Standard Frames. In any case for

- 10 -

all message bits, which shall not be included in the acceptance filtering (e.g. if groups

of messages are defined for acceptance), the Acceptance Mask Register must contain

a “1” at the corresponding bit position.

If a message doesn’t contain data bytes (e.g. in a Remote Frame or if the Data

Length

Code

is

zero)

but

data

bytes

are

included

in

the

acceptance

filtering,

such

messages are accepted, if the identifier up to the RTR bit is valid.

4.2 Functions for CAN Communications

The steps to be taken for establishing communication via the CAN bus are:



a

fter power

-on of the system

–

setting up the host controller with respect to hardware and software

links to the SJA1000

–

setting up the CAN controller for the communication with respect

to the selection of mode, acceptance filtering, bit timing etc.

–

to

be done also after a hardware reset of the SJA1000



during the main process of the application

–

prepare

messages

to

be

transmitted

and

activate

the

SJA1000

to

transmit them

–

react on messages received by the CAN controller

–

react on errors occurred during communication

Figure 11 shows the general flow of a program. In the following paragraphs the

flows, which refer directly to controlling the SJA1000, are described in more detail.

4.2.1 Initialization

As mentioned before, the stand-alone CAN controller SJA1000 has to be set up

for

CAN

communication

after

power-on

or

after

a

hardware

reset.

Furthermore

the

SJA1000 may be re-configured (re- initialized) during operation by the host controller,

which

may

send

a

(software)

reset

request.

The

flow

is

given

in

Figure

12.

A

programming

example

using

an

80C51

microcontroller

derivative

is

given

in

this

chapter.

- 11 -

After power-on the host controller runs through its own special reset routine and

then

it

enters

the

set-up

routine

for

the

SJA1000.

As

the

part

“configure

control

lines...” of Figure 11 is specific to the used microcontroller, it can

not be discussed in

general in this place. However, the example in this chapter shows, how to configure

an 80C51 derivative.

For the following description of the initialization processing see Figure 12. It is

assumed, that after power-on also the stand-alone CAN controller gets a reset pulse

(LOW

level)

at

the

pin

17,

enabling

it

to

enter

the

reset

mode.

Before

setting

up

registers

of

the

SJA1000,

the

host

controller

should

check

by

reading

the

reset

mode/request flag, if the SJA1000 has reached the reset mode, because the registers,

which get the configuration information,can be written only during reset mode.

The

host

controller

has

to

configure

the

following

registers

of

the

control

segment of the SJA1000 in reset mode:





M

ode Register (in PeliCAN mode only), selecting the following modes o

f

operation for this application

–

Acceptance Filter mode

–

Self Test mode

–

Listen Only mode





C

lock Divider Register, defining

–

if the BasicCAN or the PeliCAN mode is used

–

if the CLKOUT pin is enabled

–

if the CAN input comparator is bypassed

–

if the TX1 output is used as a dedicated receive interrupt output





A

cceptance Code and Acceptance Mask Registers

–

defining the acceptance code for messages to be received

–

defining the acceptance mask for relevant bits of the message to be

compared with corresponding bits of the acceptance code





B

us Timing Registers, see also 6

- 12 -

–

defining the bit-rate on the bus

–

defining the sample point in a bit period (bit sample point)

–

defining the number of samples taken in a bit period





O

utput Contr

ol Register

–

defining the used output mode of the CAN bus output pins TX0 and

TX1 Normal Output Mode, Clock Output Mode, Bi-Phase Output Mode

or Test Output Mode

–

defining the output pin configuration for TX0 and TX1 Float, Pull-down,

Pull-up or Push/Pull and polarity

- 13 -

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